A shift register circuit for flat panel displays (e.g., liquid crystal displays, LCD) generally includes a plurality of shift registers electrically coupled together by means of cascading. These shift registers orderly generate a plurality of gate driving pulse signals for driving gate wires of LCD.
Each class of these shift registers generally includes two complementary stable modules for stabilizing signals output by a signal input unit and a signal output unit of the shift register circuit. Each of the two stable modules receives a corresponding operation signal and is enabled in a duty of the corresponding operation signal, and thus the stable module is controlled to work. Generally, the operations pulses of the two stable modules are set to be complementary. That is, when the operation signal of one of the two stable modules changes from a logic high level thereof to a logic low level thereof, the operation signal of the other of the two stable modules changes from a logic low level thereof to a logic high level thereof. Thus, when one of the two stable modules works, the other of the two stable modules does not work; and when the not working stable module begins to work, the working stable module stops working. The two stable modules alternately work to stabilize signals output by the signal input unit and the signal output unit.
However, since signal delays and Thin Film Transistor (TFT) charging time delays may be generated in the shift register circuit, when an operation signal of either one of the two stable modules changes from the logic low level thereof to the logic high level thereof, a TFT of the stable module that is used to perform potential pull-down and stabilizing operations may not be immediately switched on. That is, when one of the two stable modules stops working, the other of the two stable modules may not immediately begin to work. On the contrary, when the two stable modules are switched, a time during which both the two stable modules do not work may occur. Thus, stability of the shift register circuit may be adversely affected.